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Shenzhen Xinlicheng Technology Co.,Ltd. / 2016-10-14

In addition to Intel and CISCO, manufacturers have begun to work together to develop memory level memory solutions.

 

 

 

The demand for memory level memory interconnection structure is very urgent.

 

 

 

At present, many vendors have begun to work together to develop Gen-Z solution, a scalable high-performance bus or interconnection architecture designed to dock computers and memory.

 

 

 

The Gen-Z alliance is an open, non proprietary, transparent industry standard institution. The agency said it believed that open standards could provide a fairer competitive environment and effectively promote the promotion, innovation and adoption of new technological achievements.

 

 

 

At present, the members of this alliance include AMD, ARM, Bloom, Cavium, Cray, Dell-EMC, HPE, Huawei, IBM, IDT, Lenovo, Mellanox Technologies, Meguiar, Microsemi, Red Hat, Samsung, Seagate, SK-Hailis, Western Data Group and Sales.

 

 

 

Obviously, there are several important forces absent. Yes, first of all, data center and server CPU supply giant Intel. This is really curious. In particular, considering the development of XPoint as another developer, the company has joined it. Besides, are there any other candidates who haven't joined the company? Yes, CISCO is not on the list. As a supplier of UCS servers, we think Cisco clearly has reason to be interested in this new CPU-memory interconnection architecture.

 

 

 

Gen-Z needs to pool the memory concept.

 

 

 

According to our knowledge, "this flexible and excellent memory design architecture can provide a set of peer-to-peer interconnection system, which can easily access large-scale data while reducing the cost of use, while avoiding the various bottlenecks that are widespread today." This should further reduce storage access distance to memory access distance by using storage level memory and new programming and architecture design ideas, thus achieving significant speed improvement. The memory semantics structure treats all communication as memory operations, including loading/storing, putting/getting and atomic operations commonly used by processors. Memory semantics can optimize the load command from CPU to register storage to sub microsecond level. This is completely different from the block storage access mechanism that needs to be managed with complex and code-intensive software stacks.

 

 

 

The Alliance also issued a bulletin saying: "The rise of low-latency storage-level memory and the need for rack-scale resources mean that a new set of data access schemes must be introduced."

 

 

 

As a basic idea, memory layer is becoming more and more important nowadays, and the composability of rack size needs to be implemented with high bandwidth and low latency structure, while ensuring seamless access to the existing ecosystem without modifying or adjusting the operating system.

 

 

 

The alliance has announced several basic features of the Gen-Z interconnection scheme:

 

 

 

_High transmission bandwidth and low latency are achieved through a simplified interface based on memory semantics. Its transmission bandwidth can be extended from tens of gigabytes per second to hundreds of gigabytes per second, while the load-to-use memory latency is less than 100 nanoseconds.

 

 

 

It supports scalable memory pools and resources, enabling real-time analysis and in memory applications.

 

 

 

It has extremely high software compatibility, that is, there is no need to make any changes to the existing operating system.

 

 

 

The scale is connected from a simple low cost to a high capacity rack scale interconnection.

 

 

 

The core norms, including structure and agreement, will be finalized by the end of 2016. In addition, the Gen-Z Alliance is actively recruiting new members, and we may welcome its first batch of products in early 2017.

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